(1) Field of the Invention
This is a continuation-in-part application of U.S. patent application Ser. No. 09/618,884, filed Jul. 18, 2000, and amended in Jan. 11, 2002. This invention relates to field effect transistors, in particular to a multiple channel, ultra-linear field effect transistors.
(2) Description of the Related Art
A field effect transistor (FET) normally is a square-law device. In the current saturation of the drain current (ID) vs gate-to-source voltage (VGS) of the characteristic of a FET, the basic relationship is given as:ID=K(VGS−Vt)2  (1)where K is a transconductance parameter, and Vt is the threshold voltage. When an input voltage is applied as a change in VGS, the output current, which appears as the change in ID, does not vary linearly with VGS. This square-law relationship causes non-linearity (harmonic distortion) and limits the dynamic range of amplifiers.
In equation (1), the threshold voltage Vt is assumed to be constant, based on a uniform impurity concentration N(x) of the semiconductor substrate. This threshold voltage is the voltage required to creating a maximum depletion layer in the substrate after strong inversion.
When the substrate concentration is not uniform, equation (1) must be modified, it was revealed by R. A. Pucel in a paper “Profile design for distortion reduction in microwave field-effect transistors” Electronic Letters, vol. 14, P. 204, 1978, that the ID can be characterized in terms of the non-linear distortion components as:ID=Ido+Gm(0VGS+½gm(1)VGS2+⅙gm(2)VGS3+ . . .   (2)where gm(n) VGSn is the nth order distortion and gm(n) is the transconductance and its derivatives with respect to the gate voltage. Linear device operation occurs at signal levels (VGS˜0) or when the higher order terms have been eliminated. Signal distortion in amplifiers is due to the higher order terms, which become important at high signal levels.
To improve the linearity of a FET, the transconductance must be constant with varying gate voltage VGS. The transconductance is strongly dependent on the electron distribution in the channel of the FET. Thus the design of a linear transistor demands paying attention to carrier distribution.
A measure of the linearity of a FET is the third order intermodulation ratio (IMR), which is the ratio of the power generated in a spurious third order intermodulation signal relative to the power in the dc desired signal. IMR has been shown to be proportional to the ratio of the third order component relative the first order (fundamental) component in Equation (2). Further more, Pucel has shown that this ratio can be expressed as:IMR∝|gm(2)/gm(0)|=(κεo/q)2|d/dx(1/x3N(x)|/N(x)  (3)where N(x) is the charge distribution in the channel, κ is the relative dielectric constant, εo is the permittivity of free space, q is electronic charge and equation (3) is evaluated at the depletion edge boundary. The requirement for a highly linear device is for IMR to be small (close to 0). Therefore, from equation (3), either x3 N(x) is constant or x3 tends to infinity. The former occurs when N(x) varies as 1/x3. In the U.S. patent application Ser. No.09/618,884, we proposed to implement such a doping profile using multi-channel to achieve linearity in Hetrojunction Field Effect Transistors (HFETs). However, the invention was limited to specific doping profile in selected semiconductor materials such as InP and GaAs. Further, the lower mobilities of the HFET limit its applications to lower frequencies.
In a standard single channel High Electron Mobility Transistors (HEMTs), higher mobilities and sheet concentrations can be achieved as compared to HFETs. Therefore HEMT devices offer higher breakdown voltages and cut-off frequencies, low noise and higher power. There are numerous prior arts on single conducting channel HEMTs and its application to low noise and power applications. In U.S. Pat. No. 6,121,641 Ohno addressed the shielding of traps and suppression of short channel effect by insertion of p-type layer in a single conducting channel HEMT, and U.S. Pat. No. 5,767,539, Onda disclosed a field effect transistor having various designs for donor supply layer but with only one channel. Further, in the U.S. patents to Mishima (No. 5,633,516 ), to Nakayama (No. 5,856,685), to Hida (No. 6,049,097), and to Matloubian (No. 5,663,583) variations to the single channel HEMT such as; two charge supply layer on either side of the channel layer, different material for spacer, various compositions of buffer and or channel have been proposed. However, there is no provision that the device can improve the linearity of the drain characteristic. U.S. Pat. No. 5,739,559 (the '559) to Isheda et al discloses a HEMT device having improved linearity. The patent '559 relates to a HEMT having asymmetrical carrier supply layers sandwiching a channel layer. More specifically, the heterojunction barrier height between the lower carrier supply layer and the channel layer is greater than the heterojunction barrier height between the upper carrier supply layer and the channel layer. Further, the patent '599 discusses only a single channel HEMT and silent regarding a HFETs in general, or having multiple channels in HFET and HEMT, or any specific carrier concentration and type of doping, or different materials for the multiple channels.
U.S. Pat. No. 6,015,981 to Gluck (“the patent '981”) relates to a HFET having high modulation efficiency. FIG. 1, shows the cross-sectional view of the patent '981. As this figure illustrates, the HFET includes supply layer 3 having a doping layer 8, a layer packet 4 having multiple channels 41 and, and a supply layer 5 having a doping layer 9. The packet 4 has at least two repetitions of undoped channel 41 and undoped layer 42. The doping layers 8 and 9 serves to provide carrier concentration in the channels and doping layer 9 is characterized as having only a small number or no charge carriers. More specifically the patent '981 discloses a single doping layer 8 below the packet 4. Further the uniform doping is proposed which increases the gate to channel distance degrading the FET performance. As regards the electron concentration profile for the multiple channels HFET, the patent '981 has limited disclosure and teaches only concentration increases with distance from the gate. Further the patent is silent regarding different materials among the various multiple channels and teaches only Si/SiGe materials with GaAs/AlGaAs as an alternate material system.
Thallium (Tl) compounds of varying composition can be lattice matched to GaAs, InP and InAs. High electron mobilities have been predicted for TlP, TlAs, and TlSb (Schilfgaard et al, Applied Physics Letter, Vol. 65, pp 2714, 1994). Therefore FET with thallium compounds channels has the advantage of achieving highest gm, and cut-off frequencies exceeding the current state-of-the-art. Recently Tl compounds (U.S. Pat. No. 5,841,156 and references therein) have been proposed as detector, FET and HBT material. However, multi-channel HEMT or HFET for linearity has not been proposed.